1. Field of the Invention
The present invention is in the field of semiconductor wafers, and provides a method for preparing such a wafer for sawing to limit chippage.
2. Description of the Prior Art
When semiconductor wafers are severed into individual chips by sawing, chippage referred to as mussel chippages occur at the saw edge of the front side of the semiconductor wafer. These mussel chippages arise independently of the sawing depth with respect to the semiconductor wafer and their extent depends on various sawing parameters such as the quality of the saw blade, the age of the saw blade, the sawing rate, and the like. The chippage is also dependent upon the parameters of the semiconductor wafers such as, for example, the doping of the semiconductor in the sawing region, the type and number of surface layers, and similar factors.
The flat splinterings of semiconductors referred to as chippage can influence the component quality when the chippage width is so high that active chip regions such, for example, as a guard ring or a pn-junction are destroyed.
Previous efforts have been made to avoid the reduction in quality of the individual chips by providing correspondingly large spacing between the active regions of an individual chip and the region destroyed by the chippage at its maximum point. No crystal destruction with respect to individual chips based on invisible "micro-cracks" can be determined outside of the visible fracture zone in the region of the chippage by means of an anisotropic etching such as a so-called "Sirtl-etch".
In the miniaturization of semiconductor components, it is important to save space and therefore the space on the surface of a semiconductor wafer should be utilized to the fullest extent. Consequently, the present invention seeks to reduce the width of the sawing track without reducing the quality or the yield of the individual chips obtained from a semiconductor wafer by sawing.
In accordance with the present invention, there is provided a method for preparing a semiconductor wafer for sawing to limit chippage upon sawing into individual pieces which involves applying a dielectric layer at least on portions of the wafer in the form of a border on the margins of those portions which are to form individual parts, the dielectric layer being applied under conditions such that the border exerts a tensile stress on the semiconductor surface, the border providing a symmetrical tensile stress distribution for limiting the chippage of the semiconductor material during sawing.
The advantages of the invention shall be set forth in a succeeding portion of the Specification with reference to silicon and silicon compounds. The invention, however, is not limited to employing silicon semiconductor wafers or to silicon compounds. On the contrary, any semiconductor wafer in combination with chemical silicon compounds or in combination with dielectric layers can be handled with the method of the present invention.